A New MAC Design Using High-Speed Partial Product Summation Tree
A novel multiplication algorithm using high-speed partial product summation tree has been presented. Some changes have been done in previous algorithms to obtain speed and better electronic parameters. In partial product generation step a new modified Booth algorithm has been proposed. In partial product reduction step a novel tree structure has been modified. In final addition step a fast adder structure using high-speed components is used. The modified Booth structure decreases the delay with the production of partial products by using the additional parallelism of conventional Booth algorithm. Multiplication is partitioned in four slices which results more speed. A new carry save addition has been used in final addition step. Modified high-speed array architecture is proposed. Simulations have been done with SPICE and some programming codes. This study has decreased transistor count by 8 percent, delay time of whole architecture has reduced 10 percent and power consumption reduction is 10 percent in compare with other previous designs.
adder arithmetic CMOS counter VLSI
P. Asadee
Islamic Azad University Varamin-Pishva branch, Iran
国际会议
北京
英文
1557-1560
2009-08-08（万方平台首次上网日期，不代表论文的发表时间）