Power Consumption Reduction in CPU Datapath using a Novel Clocking Scheme
Power consumption and performance are the crucial factors that determine the reliability of a CPU. In this paper, we discuss about some techniques that can be used for Instruction Level Parallelism which enhances the performance of the CPU by reducing the CPI there by reducing power consumption. We have also discussed about the power saving scheme using proper clocking strategies. We have mainly focused on implementing the simplified RISC pipeline datapath in HDL using two different clocking schemes to reduce the power consumption. We have adopted a new method which uses dual edge triggered clock that can decrease the power consumption of a pipelined datapath considerably, without sacrificing the throughput of the CPU. Finally, we have given the experimental result for our implementation of simplified RISC datapath.
ILP power LDPR BHT BTB dual edge triggered clock RISC pipeline datapath
Rajesh Kannan Megalingam Shekhil Hassan T Vivek P Ashwin Mohan Tanmay Rao M.
Amrita Vishwa Vidyapeetham, Amritapuri, Kollam - 690525, Kerala, India
国际会议
北京
英文
1850-1854
2009-08-08（万方平台首次上网日期，不代表论文的发表时间）