Implementation of CORDIC Based RAKE Receiver Architecture
RAKE receiver is used in CDMA-based (Code Division Multiple Access) systems and can combine multipath components, which are time-delayed versions of the original signal transmission. Combining is done in order to improve the signal to noise ratio at the receiver. RAKE receiver attempts to collect the time-shifted versions of the original signal by providing a separate correlation receiver for each of the multipath signals. This can be done due to multipath components are practically uncorrelated from another when their relative propagation delay exceeds a chip period. This paper aims to present a system-on-chip (SoC) solution for RAKE receiver using a CORDIC hardware accelerator. The algorithm is implemented on Cyclone II FPGA device chipped on Altera DE2 board. The inbuilt NIOS II soft core processor of the FPGA device acts as the processor for processing applications. The CORDIC algorithm which computes the trigonometric functions is developed as a custom instruction for the NIOS II processor. This hardware accelerator has drastically improved the performance of the algorithm by about 70% when compared with the pure software implementation. This improvement in the performance is achieved at the cost of area. The performance of RAKE receiver is illustrated using bit error rate (BER) calculations. The RAKE receiver performance is examined and compared using maximal ratio and equal-gain combining techniques.
Field programmable gate array (FPGA) system-onchip (SoC) NIOS II processor RAKE receiver CDMA mazimal-ratio combining equal-gain combining bit error rate (BER) CORDIC
K.S.Chaitanya P.Muralidhar C.B.Rama Rao
Department of Electronics and Communication Engineering National Institute of Technology Warangal, India
国际会议
北京
英文
1884-1889
2009-08-08（万方平台首次上网日期，不代表论文的发表时间）