High Speed Hardware Implementation of SHA-512 Algorithm

摘要：

Based on the analysis of SHA-512 algorithm,a new hardware structure was proposed to implement the algorithm fast in order to meet the speed requirement in all kinds of applications. The new scheme was based on suitable transformation of the algorithm. According to it,balanced pipeline with four stages could be implemented.It shortened the critical path with retiming technique together. Thus the speed performance was improved.Implemented with the Virtex II FPGA,the proposed structure achieved a throughput of 1 950 Mbps,with system frequency of 160MHz. To our knowledge,it outperformed the other released ones up to date.

关键词： SHA-512 pipeline critical path retiming

作者: Chen Huafeng Zhuang Jianzhong

作者单位: Zhejiang University of Media and Communications,Hangzhou 310018,China

会议类型: 国际会议

会议名称: 2009 International Conference on Information,Electronic and Computer Science(2009 国际信息、电子与计算机工程学术会议)

会议地点: 青岛

会议语种:英文

页码: 87-90

在线出版日期: 2009-11-21（万方平台首次上网日期，不代表论文的发表时间）