Low Power Design of VLSI Circuits and Systems

摘要：

Power consumption is the bottleneck of system performance and is listed as one of the top three challenges in ITRS 008.Low power design can be e ploited at various levels,e.g.,system level,architecture level,circuit level,and device level. This paper first gives a brief overview for low power optimization techniques at system and architecture level,then focus discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems.

关键词： low power VLSI clocking system flip-flop

作者: Peiyi hao hongfeng Wang

作者单位: Integrated Circuit Design and Embedded System Lab,Math and Computer Science Department,Chapman Unive Broadcom Corp.Irvine,CA,USA

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 17-20

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）