Architecture Design of Variable lengths Instructions Ezpansion for VLIW

摘要：

In current Instruction set architecture(ISA) design,fixed length instructions are benefit for improving the efficiency of instruction dispatching. But in embeded computers where memory is limited, variable lengths instructions are much better in memory cost.In this VLIW (Very Long Instruction Word) architecture,a two-staged pipeline is used to expand and dispatch the variable lengths instructions.When CPU receives a packet of instructions,a fixed number of instructions expand in the first pipeline phase. In the second pipeline phase,CPU dispatch instructions which execute in the same pipeline cycle.

关键词： DSP VLIW ISA Instruction Ezpansion

作者: Yuan Liu Hu He Teng Xu

作者单位: Inst.Microelectronics,Tsinghua niversity Inst.Microelectronics,Tsinghua University

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 29-32

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）