Design of a High Reliable L1 Data Cache with Redundant Cache

摘要：

Modern high-performance processors utilize cache memory systems to tolerate the increasing latency of main memory. Along with IC technology improvement, complicated cache memory systems in processors are very vulnerable to soft errors under severe environment. to deal with multiple soft errors with little impact on hardware overhead and performance,this paper proposes a new cache memory system, in which redundant cache blocks are integrated into a set-associative LI data cache.Each redundant cache block is used to store the replica of each dirty data in correspondence with L1 data cache blocks.In order to realize the detection of multiple soft errors with little hardware overhead,a bit interleaving group parity code is adopted to detect multiple soft errors in L1 data cache blocks. Moreover,in order to increase the mapping rate between L1 data cache blocks and the redundant cache blocks,an early write-back based protocol is introduced,in which all dirty cache blocks are written back to L cache at the intervals of a determined cycle number. The proposed cache system can provide more powerful soft error protection than conventional error correction codes.E periment results show that the cache system proposed in this paper can provide replicas for almost 100 of dirty cache blocks in L1 data cache on average.

关键词： Ll data cache Multiple soft errors Reliability Redundant cache

作者: haolin Li Xinyue hang Huiqing Luo

作者单位: Institute of Information Technology,Tsinghua National Laboratory for Information Science and Technol Institute of Microelectronics,Tsinghua National Laboratory for Information Science and Technology,Ts Institute of Microelectronics,Tsinghua National Laboratory for Information Science and Technology,Ts

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 41-45

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）