A 2.84W 16port Switch ASIC for High Performance Computing Systems

摘要：

The chips structure,design trade-off,and physical implementation with power optimization of a 2.84W switch ASIC,which is targeted for large scale parallel computing systems,are introduced in this paper. The chip supports not only multi-layer,multi-function packet switching with high throughput and low latency,but also provides advanced global barrier process accelerating between its 16 full-duplex ports. At 156.25 Mhz,the chip has 83.2ns zero load latency,80Gbps port-switching and 240Gbps internal packet switching capacity with ports data throughput at 2x2.5Gbps. The ASIC has been taped-out with 0.18um/6Metal CMOS technology,and has about 20 million transistors; 12.39 mm x 12.39 mm die size;with 1053 pin flip-chip package. The first pass silicon of this Switch ASIC has successfully passed DFT,functional and system level testing.

关键词： Switch Low Power Timing Design DFT

作者: Hua Shen Ding-shan You Like Liu Jia Yang Xiao-xiao Jiang

作者单位: ASIC Group,National Center of Intelligent Computing Systems(NCIC),Institute of Computing Technologie NCIC

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 54-57

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）