Design of Multi-valued Double-edge-triggered JK Flip-flop Based on Neuron MOS Transistor

摘要：

The neuron MOS transistor (neuMOS) is a new device with multi-input gates and one floating gate.it is capable of obtaining a weighted sum calculation of multi input gates signals and then operating the threshold based on the result of summation,thereby simulating the function of biological neurons. The neuron MOS transistor characteristics about multiple input gates and the floating gate capacitance coupling effect can be used to solve the output multi-valued problem. Through studying the design principles of multi-valued logic circuit and the redundant suppression method,this paper presents a design scheme of multi-valued double-edge-triggered JK flip-flop.Compared with the conventional multi-valued JK flip-flop,this circuit has the characteristic of reduction the redundant leap of clock, low power consumption and fast speed etc.Furthermore,the proposed scheme in this paper can be further apply to design higher radix multi-valued circuits.Finally,the above designed circuit is verified by PSPICE simulation.

关键词： Neuron MOS transistor double-edge-triggered JK flip-flop multi-valued logic circuit design

作者: Yuejun Zhang Pengjun Wang

作者单位: Institute of Circuits and Systems,Ningbo University,mgbo 315211 China Institute of Circuits and Systems,Ningbo University,Ningbo 315211,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 58-61

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）