DReNoC: A Dynamically Reconfigurable Computing System based on Network-on-Chip

摘要：

A dynamically reeonfigurable computing system based on network-on-chip (DReNoC) is proposed,which consists of computing nodes and communication nodes. The computing node is a complete coarse-grained dynamically reconfigurable SoC named DReSoC. And the DReSoCs communicate with each other through on chip network routers. The proposed DReNoC has been implemented on the ALTERA sTRATIX II EP2S180 DSP development board with 48063 Combinational ALUTs. And 26211 logic registers. Experimental result of 8×8 matrix sequential matrix multiplications showed that,compared with a single-core system-on-chip (SoC) based on the standard Nios II processor, the speed-up ratio can reach 124.91.

关键词： DReNoC DReSoC reconfigurable computing network-on-chip

作者: Ying-Chun Chen Gao-Ming Du Luo-Feng Geng Duo-Li Zhang Ming-Lun Gao

作者单位: Institute of VLSI Design,Hefei University of Technology,Hefei,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 71-74

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）