T2-TAM:Reusing Infrastructure Resource to Provide Parallel Testing for NoC based Chip

摘要：

Reusing Network-on-Chip (NoC) as Test Access-Mechanism (TAM) has been adopted to transfer test data to embedded cores.However,an observation shows that compared to NoC-reuse TAM,some bus-based TAM are able to achieve better results in test time due to its fine-grained scheduling unit. This paper proposed a new TAM named Test Tree(T2). T2 TAM could be built by reusing the hardware resources of routers instead of reusing the packet-based NoC. Though implementing DFT design on routers,the T2 TAM can achieve wire utilization and adopts fine-grained basic scheduling.Besides,to address the problem of testing large number of homogeneous cores,T2 TAM is proposed to facilitate multicasting stimuli to homogeneous cores to save test time. Experimental results show that the test cycles could be reduced up to 38% in comparison with the work reusing NoC as TAM with only 0.3% DFT overhead.

关键词： Network-On-Chip DFT Test-Access-Mechanism

作者: Binzhang Fu Yinhe Han Huawei Li Xiaowei Li

作者单位: Key Laboratory of Computer System and Architecture,Institute of Computing Technology,Chinese Academy of Sciences and Graduate Uinversity of Chinese Academy of Sciences,Beijing,100190

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 91-96

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）