Transaction level model of NoC based on SystemC

摘要：

This paper presents a transaction-level on-chip communication network model,including routers and links, which can be easily employed in a system-level system-on chip simulation framework for early functional verification and architecture analysis. The model is capable of providing NoCs latency and throughput information during simulating process and developed in SystemC to achieve high simulation speed.

关键词： network on chip transaction-level model SystemC

作者: Jian Wang Hong Wang Zhi jia Yang

作者单位: key laboratory of communication and control Shenyang Institute of Automation,Chinese Academy of Scie key laboratory of communication and control,Shenyang Institute of Automation,Chinese Academy of Scie

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 97-100

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）