Speedup Analysis of Data-parallel Applications on Multi-core NoCs
As more computing cores are integrated onto a single chip,the effect of network communication latency is becoming more and more significant on Multi-core Network-on chips (NoCs).For data-parallel applications,we study the model of parallel speedup by including network communication latency in Amdahls law. The speedup analysis considers the effect of network topology,network size,traffic model and computation/communication ratio.We also study the speedup efficiency.In our Multi-core NoC platform,a real data-parallel application,i.e.matrix multiplication,is used to validate the analysis. Our theoretical analysis and the application results show that the speedup improvement is nonlinear and the speedup efficiency decreases as the system size is scaled up. Such analysis can be used to guide architects and programmers to improve parallel processing efficiency by reducing network latency with optimized network design and increasing computation proportion in the program.
speedup communication multi-core NoC
Xiaowen Chen Zhonghai Lu Axel Jantsch Shuming Chen
Microelectronics Institute,School of Computer Science,National University of Defense Technology,4100 Department of Electronic,Computer,and Software Systems,KTH-Royal Institute of Technology,SE100-44,St Microelectronics Institute,School of Computer Science,National University of Defense Technology,4100
国际会议
2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)
长沙
英文
105-108
2009-10-20（万方平台首次上网日期，不代表论文的发表时间）