Uniform Routing Architecture for FPGA with Embedded IP Cores

摘要：

A uniform routing architecture is presented,which offers CLB,IOB and IP Cores an identical routing resource. At the same time,some method is adopted to optimize routing performance. With all unidirectional segmented lines and long lines with inserted tap buffers,this architecture is up to 9.8% faster compared with long lines without inserted buffers and on average 14.9% over bidirectional lines.Simulation results demonstrate our idea.

关键词： FPGA uniform routing architecture unidirectional segmented lines long line with inserted buffers

作者: Liyun Wang Yuan Wang Liguang Chen Jian Wang Xing Chen Fang Wu Jinmei Lai Jiarong Tong

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 109-112

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）