Partially Reconfigurable Interconnection Network for Dynamically Reprogrammable Resource Array

摘要：

This paper describes an innovative regular non blocking,point-to-point, point-to-multipoint, low latency interconnection network scheme with sliding window connectivity,which allows arbitrary parallelism among large sub-systems. The area overhead of interconnect is only 30% of the chip area which is much smaller as compared to 80% in case of FPGA. The interconnection scheme is partially and dynamically reconfigurable. The configware is reduced 5.6 times by using binary encoding which allows energy efficient dynamic reconfiguration.

关键词： Interconnects CGRA Partially Reconfigurable Dynamically Reconfigurable

作者: Muhammad Ali Shami Ahmed Hemani

作者单位: School of ICT,Royal Institute of Technology,Sweden

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 122-125

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）