Fast Configuration Architecture of FPGA Suitable for Bitstream Compression

摘要：

In this paper,fast configuration architecture of FPGA suitable for bitstream compression is proposed and implemented for FDP2009-11-SOPC (FDP2OO9-11-SOPC: Fudan Programmable device 2009-11-SOPC) FPGA with sMIC 0.13 CMOS process. This circuit features an addressable configuration register and the internal frame decoder that makes a 32-bit memory cell of FPGA addressable. The improved configuration circuit which can configuration every 32bit memory cells could provide faster configuration speed and more flexible partial configuration operations. The die size of FDP2009-11-SOPC is about 6.3mm*4.5mm=28.35mm2 and the area of this configuration circuit is about 1.7mm2. The post layout simulation shows that this fast configuration circuit of FDP2OO9-11-SOPC FPGA could work correctly and efficiently and the configuration time is less than 53% of that of Xilinx Virtex11 series FPGA.

关键词： FPGA Fast Configuration Architecture Internal Frame Decode Bitstream Compression

作者: Xie Jing Wang Yabin Chen Liguang Wang Jian Wang Yuan Lai Jinmei Tong Jiarong

作者单位: National High Technology Development 863 Program of China under GrantNo.2007AA01Z285 and the Nationa National High Technology Development 863 Program of China under GrantNo.2007AA01Z285 and the Nationa

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 126-130

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）