VLSI Implementation of High-speed SHA-256

摘要：

To accelerate the speed of iterative computation for the existing SHA-256 algorithm,using 7-3-2 array compressor is proposed to reduce the critical path delay in this paper. The frequency of the proposed scheme is 1.7 times higher than other VLS1 implementations under the same process.In addition,the paper designs a new universal architecture for implementing SHA-2 algorithms. The design is synthesized with the slow library of Synopsys Design Compiler in SMIC 0.18/μm CMOS process.Its function has been verified sufficiently on FPGA.Furthermore,compared with the existing SHA-256 core,the results of the ASIC synthesis and FPGA verification are more preferable. This design is convenient to implant into SoC and embedded system with the versatile architecture and high clock frequency.

关键词： SHA-256 7-3-2 compressor critical path FPGA

作者: Ling Bai Shuguo Li

作者单位: Institute of Microelectronics,Tsinghua University,Beijing,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 131-134

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）