Design and FPGA Implementation of 3DES against Power Analysis Attacks for IC Bankcard

摘要：

The Power Analysis Attacks have become a major threat to the cryptographic chips,especially in financial fields.Many countermeasures against these attacks have been proposed,and most of these countermeasures are focused on the microcontroller-based implementations.In this paper,a novel VLSI design of 3DES circuit is achieved for IC bankcard, and Random Insertion of Dummy Cycles is used against Power Analysis Attacks.Compared with the pure 3DES circuit, the extra cost for performance and extra area are significantly lowered by design optimization. The design has been verified to be feasible by FPGA,and it can keep the secret key secure under the Differential Power Analysis Attacks when the amount of power traces is less than 22,000.

关键词： 3DES Power Analysis Attacks VLSI Random insertion of Dummy Cycles

作者: Xiuyuan Bi Liji Wu Guoqiang Bai

作者单位: Institute of Microelectronics,Tsinghua University,Beijing 100084,P.R.China Microelectronics,Tsinghua University,Beijing 100084,P.R.China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 159-162

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）