A Single Channel 2GS/s 6-bit ADC with Cascade Resistive Averaging

摘要：

A single channel 2GS/s 6-bit ADC with cascade resistive averaging is demonstrated in 0.18μm CMOS. The proposed power efficient crossing connection method of averaging resistors has less reference voltage consumed than convention with excellent offset averaging. The peak DNL and INL are measured as 0.26 LSB and 0.21 LSB,respectively. The sNDR and SFDR have achieved 34.2 and 37.5dB,respectively, with 1.22 MHz input signal and 2GS/s. The SNDR and sFDR maintain above 30 and 35dB,respectively,up to 1000MHz input signal and 900MS/s. The proposed ADC,including on chip track-and-hold amplifiers and clock buffers,consumes 570 mW from a single 1.8V supply while operating at 2GS/s.

关键词： Analog-to-digital conversion offset averaging flash interpolation

作者: Youtao Zhang Xiaopeng Li Ao Liu Ming Zhang Feng Qian

作者单位: National Key Laboratory of Monolithic Integrated Circuits and Modules,Nanjing Electronic Devices nst Integrated Circuit Laboratory,Nanjing Electronic Devices Institute,NanJing,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 195-198

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）