High speed and low power ADC design with dynamic analog circuits

摘要：

This paper discusses high speed and low power ADC design with dynamic analog circuits. An OpAmp based aDC design is no longer useful in nano-meter CMOS era and a comparator based ADC design becomes dominant for ADC design along with technology scaling. Offset mismatch and input referred noise in a comparator affects ENOB seriously. Furthermore conversion speed, energy consumption and occupied area have a serious tradeoff in ENOB. A digital offset mismatch compensation technique accommodates this trade off,however accuracy is not sufficient and more effective technique should be developed ,4n equation to estimate the input referred noise in dynamic comparator has been deduced and it suggests that the noise can be reduce by increase of load capacitance and reduction of the effective gate voltage.However higher resolution than 10 bit looks not easy. Technology development is required to realize higher resolution ADC.

关键词： ADC CMOS low power comparator

作者: Akira Matsuzawa

作者单位: Department of Physical Electronics,Tokyo Institute of Technology,S3-27,2-12-1,Ookayama,Meguro-ku,Tokyo,152-8552,Japan

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 218-221

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）