3.4GS/s 3 Bit Phase Digitizing ADC and DAC for DRFM

摘要：

This paper design and realize 3 bit phase digitizing analog-to-digital converter (ADC) and digital-to analog converter (DAC) for Digital radio frequency memory (DRFM). The instantaneous bandwidth (IBW) of the DRFM is enhanced by high sampling rate. Test results show that the highest sampling rate is 3.4GS/s and the core power dissipation of ADC and DAC is 350mW and 300mW, respectivel.

关键词： Analog-to-Digital converter Digital-to-Analog converter phase digitizing digital radio frequency memory

作者: Min Zhang Youtao Zhang Xiaopeng Li Ao Liu Feng Qian

作者单位: Integrated Circuit Laboratory,Nanjing Electronic Devices Institute,NanJing,China National Key Laboratory of Monolithic Integrated Circuits and Modules,Nanjing Electronic Devices Ins

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 226-229

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）