A 14-bit Successive-Approzimation AD Converter with Digital Calibration Algorithm

摘要：

This paper implements a 14-bit successive approximation analog-to-digital converter (SAR ADC) design. The architecture and performance of the designed ADC is described A digital calibration algorithm applied in this ADC has been emphasized in this paper. The eorrection codes of the calibrated capacitor are generated from the low bit to the high bit in the correction code generation state and are loaded in the calibration state. The digital control logic switches the capacitor array with the related correction code. The testing result indicates that the SAR ADC achieves a resolution of 14-bit at 200KSPS sampling rate.

关键词： SARADC Calibration Algorithm Correction Code Capacitor Array

作者: He Yong Wu Wuchen Meng Hao Zhou Zhonghua

作者单位: VLSI and System Lab.,Beijing University of technology,Beijing 100124 China VLSI and System Lab.,Beijing University of technology,Beijing,Beijing 100124 China Beijing DT Electronic Technology Corporation,Beijing,Beijing 100102 China VLSI and System Lab,Beijing University of technology,Beijing 100124 China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 234-237

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）