A Single-Event Transient Hardened Phase-Locked Loop in 0.18 CMOS Process

摘要：

By implementing a novel complementary current limiter (CCL),a phase-locked loop (PLL) has been developed for improved single-event transient (SET) tolerance in 0.18 μm CMOS process.Simulation results show that the CCL circuit can significantly reduce the voltage perturbation on the input of the voltage-controlled oscillator (VCO) by up to 92.8%,and reduce the recovery time of the PLL by up to 76.4% in the presence of SETs in the charge pump (CP). And it can also improve the error pulses and phase displacement of the output clock greatly.Moreover,the CCL circuit can be readily applied to other PLL topologies.

关键词： charge pump phase-locked loop RHBD single-event transient

作者: Zhao Zhenyu Zhang Minxuan Chen Jihua Guo Bin

作者单位: School of Computer Science,National University of Defense Technology,Changsha 410073,P.R.China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 284-287

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）