An LO Power Distribution Network Design for Integrated 60-GHz Transceiver on Chip

摘要：

This paper presents a local oscillation (LO) distribution network for the purpose of power splitting and distribution from a voltage-controlled oscillator (VCO) to a transmitter (Tx),receiver (Rx) and phase-locked loop (PLL) frequency synthesizer for an on-chip 60-GHz transceiver. The proposed LO distribution network architecture includes one input port and three output ports. The network circuit consists of four differential amplifiers to generate sufficient LO power and several transmission lines for power splitting and impedance matching.Since the proposed 60-GHz transceiver is based on a sub-harmonic direct-conversion architecture, the LO distribution network operates at 30-GHz frequency band.In simulation,the peak power gain of 8 dB occurs at 29.5 GHz,and the 3 dB bandwidth range is from 27.7 GHz to 32.1 GHz for each output port. The simulated output referred 1 dB compression point (OPIdB) is+7 dBm and the saturated output power is+10 dBm. The DC power consumption is 78 mW under a 1.5 V supply. The LO distribution network circuit is integrated with the 60-GHz transceiver and fabricated in 65nm CMOS.

关键词： LO sub-harmonic transceiver CMOS 60 GHz

作者: Y.Mo K.Wang F.Zhang E.Skafidas R.Evans I.Mareels

作者单位: National ICT Australia,Department of Electrical and Electronic Engineering,the University of Melbourne,VIC 3010,Australia

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 292-295

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）