An 0.35um CMOS 2.4Gb/s LVDS for high-speed DAC
In the light of application to high-speed DAC, the design and achievement of a novel high-performance CMOS LVDS receiving circuits are described in this paper. By introduction of intrinsic offset,a fixed hysteresis voltage is obtained The whole circuit doesnt need any local feedback,and the high-speed performance of the original circuit doesnt change with introduction of hysteresis voltage. Therefore the circuit has twofold advantages: a stable hysteresis voltage and a high-speed operation. The circuit was developed in chartered 0.35urn cMOS process technology. The tested results showed that the circuit worked stably at an operational voltage of 3.3 V at a transmission speed of 2.4Gb/s. The chip size of the circuit was 0.021mm2, and the power consumption of the circuit was 8mW1.
LVDS D/A converter high-speed I/O
Xingfa Huang Liang Li Kaikai Xu Ruzhang Li Cheng Shu
National Labs of Analog Integrated Circuits,Chongqing,China Department of Electrical Engineering California State University Fullerton
国际会议
2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)
长沙
英文
317-319
2009-10-20（万方平台首次上网日期，不代表论文的发表时间）