A 15-μs Fast-Locking Frequency Synthesizer for Reconfigurable Wireless Systems

摘要：

A fast-locking wideband CMOS frequency synthesizer for reconfigurable wireless applications is presented. An analog coarse tuning loop with a large loop bandwidth is used for fast locking,and new adaptive loop filters are proposed to stabilize the coarse tuning voltage when the loop is switched off. The frequency synthesizer with a 1.95-2.6 GHz frequency range is fabricated in 0.18 μm CMOS process and achieves a settling time of 15-μs with loop bandwidth of 100 kHz.So far as we know,this is the fastest locking speed for wideband frequency synthesizers with the same loop bandwidth.

关键词： Frequency synthesizer settling time dualloop wideband

作者: Junhua Liu Huailin Liao Ru Huang

作者单位: Institute of Mieroelectronics,Peking University,Beijing,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 359-362

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）