Design Trade-Offs for Digitally Equalized CMOS RF Transmitter
A digital linearity and efficiency enhancement technique of CMOS direct-conversion transmitter is reviewed in this paper,with the involved analog as well as digital design trade-offs explored It is shown that the 1/Q mismatch and memoryless nonlinearities of the transmit path,including the potentially severe amplitude and phase distortions of the power amplifier (PA),can be effectively compensated by a digital,two-dimensional look-up table (2-D LUT) adapted by an LMS algorithm,resulting in a highly efficient transmitter architecture with minimum analog and RE complexity.
Power amplifier adaptive digital equalization RF transmitter look-up table memoryless nonlinearity
Yun Chiu Dae Hyun Kwon Hao Li
Electrical and Computer Engineering Department,University of Illinois at Urbana-Champaign,Urbana,IL 61801 USA
国际会议
2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)
长沙
英文
371-374
2009-10-20（万方平台首次上网日期，不代表论文的发表时间）