A Spread Spectrum Clock Generator with Phase-rotation Algorithm for 6Gbps Clock and Data Recovery

摘要：

A low jitter phase-lock-loop (PLL) and a proposed spread-spectrum clock method for Serial ATA with phase rotation is presented. The low jitter PLL uses error amplifier to resolve the current mismatch in charge pump and the 3rd order loop filter is adopted to reduce the reference spur. A passive resistance is presented in our design to reduce the Kvco. Our spread spectrum clock generator (SSCG) for Serial ATA specification is down spread 5000 ppm with a triangular waveform and the modulation frequency is 30-33Kttz.Spread-spectrum technique using PLL with a △ Σ modulator and phase rotation algorithm is reported. The proposed circuit has been designed in a 90-nm CMOS process. The non-spread spectrum clocking has a peak to peak jitter of 512fs and consumes 5.87mW at 1.4GHz. The EMI reduction is about 19.24dB.

关键词： PLL serial ATA EMI SSCG

作者: Chi-Hsien Lin Yen-Ying Huang Shu-Rung Li Yuan-Pu Cheng Shyh-Jye Jou

作者单位: Department of Electronics Engineering,National Chiao-Tung University,Hsinchu,Taiwan R.O.C

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 387-390

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）