PAC Duo SoC Performance Analysis with ESL Design Methodology
PAC Duo System on Chip (SoC) is a high performance and low power multimedia tri-core SoC designed at SoC Technology Center (STC) of Industrial Technology and Research Institute (ITRI).We are facing a situation of continuous increasing of design complexity,when we integrate more components and try to evaluate the system performance or do further architecture exploration.In this paper,we present a system-level virtual platform and simulation environment for performance profiling and evaluation based on electronic system-level (ESL) design methodology. Through the fine-tuning of functionality, timing, and simulation speed,the resulted virtual platform achieves a high accuracy with a less than 10% of the cycle count error against RTL simulation with an 80～150 times simulation performance improvement.With this methodology,the system function evaluation and performance profiling can be easily realized.We also show the experimental results for various multimedia applications compared with RTL simulation and further demonstrate how the virtual platform successfully predicts the real chip performance of the evaluation board.
parallel architecture core (PAC) system on chip (SoC) electronic system-level (ESL) transaction-level modeling(TLM) performance evaluation
I-Yao Chuang Chi-Wen Chang Tso-Yi Fan Jen-Chieh Yeh Kung-Ming Ji Jui-Liang Ma An-Yeu Wu Shih-Yin Lin
SoC Technology Center,Industrial Technology Research Institute,Hsinchu,31040 Taiwan Department/Graduate Institute of Electrical Engineering,National Taiwan University,Taipei,10617 Taiw
国际会议
2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)
长沙
英文
399-402
2009-10-20（万方平台首次上网日期，不代表论文的发表时间）