Efficient Floor-Planning Methodology for the Jasper Forest SoC on a 45 Nanometer Process

摘要：

Floor-planning is usually one of design bottleneck for physical design convergence.For a complex soC such as Jasper Forest,being concurrently developed and integrated with a leading edge CPU (Nehalem),floor planning becomes even a bigger challenge to convergence on a very tight schedule. This paper highlights the floor-plan methodology and implementation details for Jasper Forest, with 782 million transistors,optimized for a 45 nm process. The methodology features an abutment LEGO structure floor plan partitioning,a hybrid look-ahead floor-planning methodology,a semi-custom global clock tree construction, and Correct-by-Construction practices. These unique and innovative floor-planning methods enabled us to appropriately decouple complex design processes,minimize design dependencies,avoid non value added steps,and reduce the number of iterations to achieve the business goal of fast turnaround time with fewer resources.

关键词： Floor planning partitioning global clock tree design SoC

作者: Yuyun Liao Nishi Raman Liping Kong Jung-Yueh Chang

作者单位: Intel Corporation,Chandler,AZ 85226 USA Corporation,Chandler,AZ 85226 USA

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 407-410

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）