A Study and Design of CMOS H-Tree Clock Distribution Network in System-on-Chip

摘要：

A design of a low skew clock distribution network is presented based on the TSMC 0.18μm CMOS technology. This work first investigated various aspects in designing a clock distribution network. After that,the design methodology for the chosen H-Tree clock network topology is presented. A series of design performance analyses such as clock delay,skew,rise and fall time,supply voltage and temperature variations and power consumption were compared for both pre-layout and post-layout simulation results.Pre-layout and post-layout simulation results validated the 3-segment π-model. The clock network designed is able to operate up to maximum clock speed of 1.1GHz for a 1×1mm2 chip with zero skew.

关键词： Clocks CMOS digital integrated circuits

作者: Wei-Khee Loo Kok-Siang Tan Ying-Khai Teh

作者单位: Faculty of Engineering,Multimedia University,63100 Cyberjaya,Malaysia Faculty of Engineering.Multimedia University,63100 Cyberjaya,Malaysia

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 411-414

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）