The Design of a Sub-Nanojoule Asynchronous 8051 with Interface to Ezternal Commercial Memory
In this paper,we present the design of an asynchronous 80 1 microcontroller with interface to e ternal commercial memory. The design consists of an asynchronous core implemented using dual-rail four-phase protocol, a 1 8 byte internal asynchronous RAM and other synchronous peripherals including interrupts,timers and serial port. The asynchronous core contains all standard 80 1 instructions e cept for multiplication and division. The interface to e ternal commercial ROM and SRAM is controlled by two internal counters with ad ustable overflow values to accommodate potentially variable clock source and e ternal memory access time. An acknowledge signal is generated once the counter overflows which indicates the completion of a read write operation. The chip is implemented using Austria Micro Systems (AMS) 0.m technology.It is able to operate at 0.MIPS and consume 1 1pJ Instruction at 1.0V supply. Another two-stage pipelined version designed later operates at 0.MIPS and consumes 180pJ Instruction at the same supply.
Low-Power Asynchronous 1,Ezternal memory interface Asynchronous RAM
Chao Xue Xiang Cheng Yang Guo Yong Lian
National University of Singapore National University of Defense,Tech
国际会议
2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)
长沙
英文
427-430
2009-10-20（万方平台首次上网日期，不代表论文的发表时间）