All Digital Wireless Transceiver Using Modified BPSK and 2/3 Sub-sampling Technique

摘要：

In this paper an all digital wireless transceiver is presented,with a proposed technique for data recovery.Communication is carried out on carrier frequency of 100 MHz with a local clock of 2/3 carrier frequency on the receiver side used to sub-sample incoming wireless signal and understand transmitted data. A modified BPSK is employed,which stretches periods of phase change to enable data recovery in our all digital circuit without clock recovery. The transceiver is implemented and tested on FPGA connected to coils to perform actual short range wireless communication. Our design uses no analog components and our target is to consume as low power as possible, which makes it suitable for low power applications like wireless image sensor nodes.

关键词： All digital wireless transceiver sub-sampling

作者: Sanad Bushnaq Toru Nakura Makoto Ikeda Kunihiro Asada

作者单位: Electronics Engineering,University of Tokyo VLSI Design and Education Center (VDEC),University of Tokyo Electronics Engineering,University of Tokyo VLSI Design and Education Center (VDEC),University of To

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 469-472

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）