A Low Power High Date Rate ASK IF Receiver

摘要：

A low power high data rate ASK IF receiver is proposed.It consists of one digital-control AGC loop and an ASK detector.By utilizing the scrambler concept in the digital communication systems, the gain of PGA in the AGC loop is adjusted discretely by a gain control block to eliminate the multi-digit A/D converter. The ASK IF receiver has been implemented in 0.18μm CMOS and the overall power consumption is 2.175mW with a supply voltage of 1.8V. The operating frequency is IOM,and the data rate is 2Mbps. The amplitude of detectable input signal can range from 5μV to 900mV.

关键词： CMOS AGC ASK demodulator Low power

作者: Xiaoman Wang Baoyong Chi Zhihua Wang

作者单位: Institute of Mieroelectronies,Tsinghua University,Beijing 100084,China Institute of Microelectronics,Tsinghua University,Beijing 100084,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 473-476

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）