High-Speed Reed-Solomon Errors-and-Erasures Decoder Design with Burst Error Correcting
Reed-Solomon code has been extensively studied in both academia and industry for its wide applications in digital communication and data storage systems.However,existing works are focused on errors-alone or errors-and-erasures decoding.In this paper,starting from a recent theoretical work,an efficient VLSI architecture is developed and implemented by exploring pipeline-interleaving inversionless Berlekamp-Massey algorithm,which not only keeps original RS codes error or error-and-erasure correcting capability,but also has significantly improved burst error correcting capacity. The new architecture,denoted as PI-iBM-BEC,is shown to achieve better error correcting capacity and delivers higher throughput with relatively lower hardware complexity compared with prior arts.
Reed-Solomon codes burst error correcting errors-and-erasures VLSI pipeline interleaving
Bo Yuan Jin Sha Li Li Zhongfeng Wang
Institute of VLSI Design,Nanjing University,Nanjing 210093,China Broadcom Corporation,Irvine,CA 92617 USA
国际会议
2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)
长沙
英文
485-488
2009-10-20（万方平台首次上网日期，不代表论文的发表时间）