An Area-efficient and degree-computationless BCH Decoder for DVB-S2

摘要：

This paper presents an area-efficient BCH decoder for DVB-S2 system. The proposed architecture can support all 11 code rates in DVB-S2.Based on the modified Euclidean algorithm (MEA),The BCH decoder has a low hardware complexity with the folding and degree computationless architecture in key equation solver (KES) block.Further more,the multiplier in Galois Field is also optimized to reduce the hardware complexity. The proposed decoder requires at least 16% fewer gates than the conventional RS/BCH decoders and can work up to 277MHz,which meets the speed requirements of the system.

关键词： BCH decoder DVB-S2 MEA degree computationless architecture

作者: Zhou Chen Yulong Zhang Yan Ying Chuan Wu Xiaoyang Zeng

作者单位: State Key Lab of ASIC & System,Fudan University,Shanghai 201203,P.R.China the department of Micro-electronics,Fudan University,Shanghai 201203,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 489-492

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）