Design and Implementation of a Multi-Mode Interleaver/Deinterleaver for MIMO OFDM Systems
This paper presents a novel design strategy and a new architecture for multi-mode interleaver/deinterleaver,which are capable to implement any of the interleaving processes defined in the IEEE 802.11 a/g/n,802.16d/e, and Hiper LAN/2 wireless standards. To enable a comparison,a 36-mode interleaver/deinterleaver fully compliant to IEEE 802.11n applications is presented. The proposed design is implemented in SMIC 0.13um 1.08V 1P6M CMOS technology. The maximum operating frequency is 350 MHz and the corresponding power dissipation is 9.27mW. The core size is 0.0649 mm2. This presented architecture achieves a significant reduction of silicon area and power consumption compared with other current approaches.
IEEE 802.11n interleaver deinterleaver multiple-input multiple-output(MIMO)orthogonal frequency-division multiplezing(OFDM)
Zhen-dong Zhang Bin Wu Yong-xu Zhu Yu-mei Zhou
Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China
国际会议
2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)
长沙
英文
513-516
2009-10-20（万方平台首次上网日期，不代表论文的发表时间）