A Highly Efficient Inverse Transform Architecture for Multi-Standard HDTV Decoder

摘要：

This paper presents a VLSI implementation for inverse transforms of H.264/AVC,AVS and MPEGI/2/4. Based on distributed arithmetic,the inverse transforms of the three video coding standards share the unique architecture,which achieves less hardware cost and better decoding efficiency than separate designs. The core element of the distributed arithmetic is implemented with pipelined architecture,where only table accessing,shift and accumulation are needed. To optimize the efficiency of inverse transformation,a zero pre-detecting scheme is used in the proposed architecture. The distributed arithmetic tables are organized as differential code to reduce almost half of the ROM size. With our dedicated modularization,the proposed architecture is suitable for multi-standard HDTV applications.

关键词： Inverse Transform Distributed Arithmetic Architecture H.264/AVC AVS and MPEG 1/2/4

作者: Hang Zhang Peilin Liu Yu Hong Dajiang Zhou Satoshi Goto

作者单位: Department of Electronic Engineering,Shanghai Jiao Tong University,Shanghai 200240,China Graduate School of Information,Production and Systems,Waseda University,2-7 Hibikino,808-0135,Japan

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 525-528

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）