An Optimized △Σ Fractional-N Frequency Synthesizer for CMOS UHF RFID Reader

摘要：

A novel 3-bit 3rd-order △Σ fractional-N frequency synthesizer specialized for monolithic UHF band radio frequency identification reader is implemented in 0.18μm CMOS technology. The phase noise requirements are recapitulated for the zero-IF transceiver architecture and EPC global C1G2 and ETSI multi-protocol operation. The measurement results show that the synthesizer phase noise at 200 kHz offset is suppressed by the additional zero configuration in delta-sigma modulator(DSM)s noise transfer function with acceptable in-band noise penalty. The measured phase noise is -102 and-126.5dBc/Hz at 200 kHz and 1 MHz offsets from 900 MHz operation frequency while drawing 9.6 mA from 1.8V power supply.

关键词： CMOS delta-sigma(△Σ) fractionaI-N synthesizer ultra-high-frequency radio-frequency identification (UHF RFID)

作者: Chunqi Shi Runxi Zhang Zongsheng Lai

作者单位: Institute of Microelectronic Circuits and Systems,East China Normal University Shanghai,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 545-548

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）