Probability of Calculation Failures by Soft Errors in an Embedded Processor Core
We are developing a 32-bit embedded processor core with soft error detection and recovery mechanisms. Adding a parity bit into pipeline registers makes it possible to detect Single Event Upset in an processor core.Detection of 2-bit and less Multiple Bit Upset and automatic correction of Single Event Upset can be done with Single Error Correction and Double Error Detection code. These soft-error detection/recovery mechanisms cause cost/performance degradation.n this paper.probability of serious calculation failures occurred by SEU in an MIPS R3000 compatible processor core is evaluated.We investigate the probability using Register Transfer Level simulation. The result shows that impacts of SEU to calculation result differ much,when SEU happens in a Program Counter,an Instruction Register or register files.Soft error detection/recovery mechanism of an embedded processor core can be selected automatically when permitted soft error rate of an application program is given as a specification.
Embedded Processor Error detection Soft Error
Hiroyuki Kanbara Hiroyuki Okuhata Masanao Ise Ryota Kinjo Yuki Toda
ASTEM RI and Synthesis Corp.Osaka,556-0011,JAPAN Graduate School of Energy Science,Kyoto University,Kyoto,611-0011,JAPAN School of Science & Technology,Kwansei Gakuin University,Sanda,669-1337,JAPAN
国际会议
2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)
长沙
英文
601-604
2009-10-20（万方平台首次上网日期，不代表论文的发表时间）