Automatic Configuration Generation for A SOCCo-Verification Technology Based FPGA Functional Test System

摘要：

A FPGA-under-test has to be configured before it is tested.However,traditional configuration for a FPGA-under-test is time consuming due to the fact that the configuration has to be conducted manually many times until each resource of FPGA is not left behind. Automatic configuration generation for a FPGA-under-test implemented by an in-house SOC co-verification technology based FPGA functional test system is proposed and presented in the paper.Software side will dispatch configuration order to hardware side,while hardware side will produce configuration timing and inform software side the FPGA-under-test is available.Configuration bit-stream data will be transmitted to hardware side.Depending on the information of status register of configuration module,software part can determine whether configuration has been implemented or not.Experimental result demonstrates that it only takes about 1.5 seconds for one configuration.

关键词： FPGA SOC co-verification,configuration generation test

作者: A.W.Ruan Y.B.Liao P.Li W.Li W.C.Li

作者单位: State Key Laboratory of Electronic Films and Integrated Devices,University of Electronic Science and Technology of China,Chengdu,610054,China

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 605-608

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）