Soft Error Filtered and Hardened Latch

摘要：

this paper presents a low-power soft error-hardened latch suitable for reliable circuits. The proposed circuit uses redundant feedback loop to protect latch circuit against soft error on the internal nodes and skewed CMOS to filter out transients resulting from particle hit on combinational logic. The proposed circuit has low power consumption,enhanced setup time and lower timing overhead The HSPICE post-layout simulations in 90nm CMOS technology reveals that circuit is able to recover from single particle strike on internal nodes and tolerates input SETs up to 130ps of duration.

关键词： soft-error reliability latch skewed CMOS

作者: Hossein Karimiyan Alidash Sayed Masoud Sayedi Hossein Saidi Vojin G.Oklobdzija

作者单位: ECE Department of Isfahan Univ.of Tech.,Isfahan 84154-83111,Iran Univ.of Texas at Dallas,TX 75080,USA

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 613-616

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）