Prospects for Variation Tolerant SRAM Circuit Designs

摘要：

This paper discusses on prospects for area-scaling capabilities of many kinds of SRAM margin assist solutions for VT variability issue,which are based on various efforts by not only the cell topology changes from 6T to 8T and 10T but also incorporating of multiple cell terminal biasing and timing sequence controls of read and write. The various SRAM solutions are analyzed in light of an impact on the required area overhead for each design solution given by ever increasing VT -random variation (σ VT),resulting in a slowdown in the sRAM scaling pace.It has been shown that 6T SRAM cell will be allowed a long reign even in 15nm process node if σVT can be suppressed to<70mV thanks to EOT (Effective Oxide Thickness) scaling for LSTP (Low standby Power) process,otherwise 10T and 8T with read modify write (RMW) will be needed after σVT becomes >85mV and 75mV,respectively.

关键词： SRAM scaling SRAM design solution SRAM scaling trend deeper nanometer-scale

作者: Hiroyuki Yamauchi

作者单位: Fukuoka Institute of Technology,Fukuoka,Japan,811-0295

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 621-624

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）