A 90-nm CMOS Embedded Low Power SRAM Compiler

摘要：

In this paper a highly flexible low power single port static Random Access Memory (SRAM) compiler design is presented. The Divided Word Line (DWL) and Divided Bit Line (DBL) scheme were implemented for reducing active power.Particular emphasis was put to decrease standby power consumption in word line driver. The forced-stack devices as pulse generation element was introduced for sensing enable. This guarantees SRAM can work in low voltage without losing design margin. A test-chip with 17 embedded SRAMs has been fabricated in UMC 90-nm low leakage CMOS logic proces.

关键词： Low power SRAM compiler divided word line divided bit line forced-stack device part power-gating replica technique self-timing

作者: Zhao-Yong Zhang Chia-Cheng Chen Jian-Bin Zheng

作者单位: Memory Design Department,AiceStar Technology Corporation,Suzhou,China Module Intellectual Property Development,Faraday Technology Corporation,Hsin-chu City,Taiwan

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 625-628

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）