Low-Area 1-kb Multi-Bit OTP IP Design

摘要：

In this paper 1-kb multi-bit OTP IP,which is non-volatile memory,is designed for a power management 1C. A conventional multi-bit OTP cell uses isolated NMOS transistor,but the cell size is large in the BCD process.So,PMOS transistor is used instead of the isolated NMOS transistor as antifuse,and the cell size is minimized by optimizing the size of PMOS transistor.In addition,an ESD protection circuit is added to prevent the case that any cell is programmed by high voltage at ESD test. The 1kb OTP IP is designed using Dongbus 0.18/μm BCD process and the layout size of the IP is 160.490 ×506.255 μm.

关键词： Multi-bit OTP PMOS antifuse ESD protection thin gate ozide breakdown

作者: Li-yan Jin Tae-Hoon Kim Cheon-Hyo Lee Pan-Bong Ha Young-Hee Kim

作者单位: Department of Electronic Engineering,Changwon National University,Korea Electrical Engineering Department,Korea Aviation Polytechnic College,Korea

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 629-632

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）