Characterization of WID Delay Variability Using RO-array Test Structures

摘要：

Characterization of delay variability on a real silicon is one of key challenges for DFM&Y.We have measured D2D and WID delay variability in 65nm,90nm,and 180nm processes using RO-array test structures,and decomposed WID variability into three components of random,deterministic,and systematic variation in descending order of magnitude for all three processes at a single-gate level.

关键词： delay variability test structure RO-array WID variation D2D variation SSTA

作者: Hidetoshi Onodera Haruhiko Terada

作者单位: Department of Communications and Computer Engineering,Kyoto University,Kyoto 606-8501,Japan,and JST, Kyoto University,and now with Sony Corp

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 658-661

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）