Power-Efficient and Fault-Tolerant Circuits and Systems
As devices become smaller,circuits and systems are more vulnerable to sofi errors caused by radiation and other environmental upsets.Fault tolerance measured by mean time to failure (MTTF) is desired,especially if no extra area,power and delay and little change of the existing design flow are introduced.Using FPGA as a testbed,this paper first presents fault tolerance techniques applying (1) logic dont care and path re-convergence (ROSE) and (2) in-place logic re-writing (IPR).Both increase MTTF by 2X with little or no overhead.Particularly,IPR does not change circuit placement and routing,and can be readily used with the existing industrial design flow.It also leads to a self evolution method to enhance fault tolerance for FPGA based circuits and systems. The ideas presented in the paper can be extend to handle regular logic fabrics,which are natural to nano technologies and are also preferred by design for manufacturability (DFM) in scaled CMOS technologies.
Field Programmable Gate Array Fault Tolerance Logic Synthesis
Lei He Yu Hu
Electrical Engineering Department,University of California Los Angeles (UCLA),Los Angeles,CA 90066,USA
国际会议
2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)
长沙
英文
708-713
2009-10-20（万方平台首次上网日期，不代表论文的发表时间）