Layout Optimizations for Double Patterning Lithography

摘要：

Deep sub-wavelength lithography is one of the most fundamental challenges for future scaling beyond 32nm as the in dustry is currently stuck at the 193nm lithography.Many ingenious technologies/tricks are developed to push the limit of 193nm lithog raphy,e.g.,immersion lithography and computational lithography. But they may not be sufficient for 22nm patterning.Meanwhile,next generation lithography,such as EUV (Extreme Ultra-Violet) lithogra phy may not be available for mass production in the near future. As a practical solution,double patterning lithography (DPL) has become a leading candidate for 22nm (and likely 16nm) lithography process. DPL poses new challenges for overlay control,layout decomposition, and up-stream physical designs.In this paper,we will discuss some recent advancements and challenges in layout decompositions and DPL friendly layout optimizations.

关键词： Double Patterning Lithography Decomposition Detailed Routing Redundant Via Layout Optimization

作者: David Z.Pan Jae-seok Yang Kun Yuan Minsik Cho Yongchan Ban

作者单位: Dept.of ECE,The University of Texas at Austin,Austin,TX 78712 USA

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 726-729

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）