A proposal for a capture method of low power design intent

摘要：

The logic designer examines a sequence of the power gate as specifications, and is decided The logic designer should take responsibility.But big a factors in UPF and CPF is decided by a reason of the chip construction,as if divide it at the time of the insertion of the isolation cells,the insertion of the always on buffer,and the power switch capacity with placement location. These are not responsibility by the logic designers. The UPF and CPF require to the logic designer to define these in as the specifications. Then what will the specifications of the power supply interception that designer should define be originally? I make the thing which should examine the specifications about the power supply interception that I can select as each process by the process of the design as linkage,design intent clear and want to suggest a proposal for the future EDA tool.

关键词： UPF CPF low power design intent

作者: Yoshio Inoue

作者单位: Renesas Technology Corp.,Tokyo,Japan

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 775-776

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）