Multi-Gate-Length versus Dual-Gate-Length Biasing for Active Mode Leakage Power Reduction: Benchmarking and Modeling

摘要：

Multi-gate-length (MGL) and dual-gate-length (DGL) biasing techniques are investigated for timing constraint-aware active mode leakage power reduction of VLSI circuits.Key design and technology characteristics essential for leakage reduction are identified and utilized to carry out a Monte-Carlo-based study to benchmark MGL against DGL over different design styles and various technologies.Extensive results indicate that MGL offers generally modest to small advantage over DGL.Novel analytical models have been developed to describe leakage reduction capability of DGL/MGL and reveal its dependences on key design/technology characteristics to quantitatively assess the cost-benefit trade-off of implementing DGL/MGL.

关键词： Leakage Dual-gate-length Multi-gate-length Monte-Carlo Optimization Modeling

作者: Qiang Chen Sridhar Tirumala

作者单位: Synopsys,Mountain View,CA 94043 USA

会议类型: 国际会议

会议名称: 2009 IEEE 8th International Conference on ASIC(第八届IEEE国际专用集成电路大会)

会议地点: 长沙

会议语种:英文

页码: 781-784

在线出版日期: 2009-10-20（万方平台首次上网日期，不代表论文的发表时间）